1.
Pramesty KAP, Darmawan B, Ch S. Rancang Bangun Modul Percobaan Gerbang Logika Dan Flip-Flop Di Labolatorium Elektronika Dan Digital Fakultas Teknik Elektro Universitas Mataram. JEITECH [Internet]. 2024 Jul. 31 [cited 2025 Aug. 22];2(2):1-7. Available from: https://journal.unram.ac.id/index.php/jeitech/article/view/3361